---------------------------------------------------------------------------
-- Company     : Vim Inc
-- Author(s)   : Fabien Marteau
-- 
-- Creation Date : 24/04/2008
-- File          : Top_tb.vhd
--
-- Abstract : 
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

use work.atmega_pkg.ALL;

---------------------------------------------------------------------------
Entity Top_tb is 
---------------------------------------------------------------------------
end entity;


---------------------------------------------------------------------------
Architecture Top_tb_1 of Top_tb is
	---------------------------------------------------------------------------
	CONSTANT HALF_PERIODE : time := 10 ns;  -- Half clock period of 50MHz
	CONSTANT ATMEGA_HALF_PERIODE : time := 31.1 ns;  -- Half clock period of 50MHz

	component Top
		port (
			-- Atmega128 port
			Address_H  : in std_logic_vector( 7 downto 0);
			DA         : inout std_logic_vector( 7 downto 0);
			ALE        : in std_logic ;
			RD         : in std_logic ;
			WR         : in std_logic ;
			DIR_buffer : out std_logic ;

			-- Clock and reset
			clk        : in std_logic ;
			reset_n    : in std_logic ;

			-- Output
			LED        : out std_logic ;
			pwm        : out std_logic ;
			pwm_dir    : out std_logic 

			);
	end component;

	signal	Address_H  : std_logic_vector( 7 downto 0);
	signal	DA         : std_logic_vector( 7 downto 0);
	signal	ALE        : std_logic ;
	signal	RD         : std_logic ;
	signal	WR         : std_logic ;
	signal	DIR_buffer : std_logic ;
	signal	clk        : std_logic ;
	signal	reset_n    : std_logic ;
	signal	LED        : std_logic ;

	signal atclk : std_logic ;
	signal address : std_logic_vector( 15 downto 0);

begin

	reset_n <= '0', '1' AFTER 4*HALF_PERIODE;
	-- Clock
	Clockp : process
	begin
		clk <= '1';
		wait for HALF_PERIODE;
		clk <= '0';
		wait for HALF_PERIODE;
	end process Clockp;

	AtmegaClk : process
	begin
		atclk <= '1';
		wait for ATMEGA_HALF_PERIODE;
		atclk <= '0';
		wait for ATMEGA_HALF_PERIODE;
	end process AtmegaClk;

	stimulis : process
		variable value : std_logic_vector( 7 downto 0);
	begin
		Address_H  <= (others => '0');
		DA         <= (others => 'Z');
		ALE        <= '0';
		RD         <= '1';
		WR         <= '1';
		wait for 50 ns;
	
		-- Write test
		atmega_write(x"1300",x"01",
			atclk,Address_H,DA,ALE,RD,WR,DIR_buffer);	

		-- Read test
		atmega_read(x"1300",value,
			atclk,Address_H,DA,ALE,RD,WR,DIR_buffer);
		assert value = x"01" report "Wrong led value read" severity error;

		wait for 10 ns;

		-- Write test
		atmega_write(x"1300",x"00",
			atclk,Address_H,DA,ALE,RD,WR,DIR_buffer);	
		-- Read test
		atmega_read(x"1300",value,
			atclk,Address_H,DA,ALE,RD,WR,DIR_buffer);
		assert value = x"00" report "Wrong led value read" severity error;

		-- Write test
		atmega_write(x"1302",x"fe",
			atclk,Address_H,DA,ALE,RD,WR,DIR_buffer);	
		atmega_write(x"1303",x"83",
			atclk,Address_H,DA,ALE,RD,WR,DIR_buffer);	

		wait for 100 us;
		-- Read test
		atmega_read(x"1302",value,
			atclk,Address_H,DA,ALE,RD,WR,DIR_buffer);
		assert value = x"fe" report "Wrong pwm LSB value read" severity error;

		wait for 100 us;
		-- Read test
		atmega_read(x"1303",value,
		atclk,Address_H,DA,ALE,RD,WR,DIR_buffer);
		assert value = x"83" report "Wrong pwm MSB value read" severity error;

		wait for 200 us;
		-- Write test
		atmega_write(x"1302",x"3f",
			atclk,Address_H,DA,ALE,RD,WR,DIR_buffer);	
		atmega_write(x"1303",x"00",
			atclk,Address_H,DA,ALE,RD,WR,DIR_buffer);	

		wait for 200 us;
		-- Write test
		atmega_write(x"1302",x"3f",
			atclk,Address_H,DA,ALE,RD,WR,DIR_buffer);	
		atmega_write(x"1303",x"80",
			atclk,Address_H,DA,ALE,RD,WR,DIR_buffer);	


		wait for 2000 us;

		assert false report "End of test" severity error;
	end process stimulis;

	connect_Top : Top
	port map (
		-- Atmega128 port
		Address_H  => Address_H ,
		DA         => DA,
		ALE        => ALE,
		RD         => RD,
		WR         => WR,
		DIR_buffer => DIR_buffer,
		-- Clock and reset
		clk        => clk,
		reset_n    => reset_n,
		-- Output
		LED        => LED

		);

end architecture Top_tb_1;

